1. Field
The present invention generally relates to a semiconductor device, which may include a ferroelectric capacitor and a semiconductor manufacturing method.
2. Description of the Related Art
Conventionally, ferroelectric memories, which are nonvolatile memory elements, are operated by bias voltages. Ferroelectric memories perform fast operations with low power consumption and retain stored information even if the bias voltages are turned off, which is preferable for memory devices. The ferroelectric memories are applied to IC cards and mobile electronic devices.
FIG. 1 is an illustration showing a cross section of a ferroelectric memory device called a stack type memory.
Referring to FIG. 1, a ferroelectric memory device 10 is called a 1T1C type (one-transistor and one capacitor) device. Two memory transistors are formed in a device region 11A isolated by an isolation region 11I formed on a silicon substrate 11, which two transistors are formed to have a common bit line.
More specifically, an n-type well is formed in the silicon substrate 11 as the device region 11A. In the device region 11A, a first MOS (metal-oxide-semiconductor) transistor having a poly silicon gate electrode 13A and a second MOS transistor having a poly silicon gate electrode 13B are formed on a gate insulating film 12A and a gate insulating film 12B, respectively.
Further, p− type LDD (lightly-doped-drain) regions 11a and 11b are formed to correspond to sidewalls of the poly silicon gate electrode 13A in the silicon substrate 11. Other p type LDD regions 11c and 11d are formed to correspond to sidewalls of the poly silicon gate electrode 13B in the silicon substrate 11. The first and second MOS transistors are formed in the device region 11A in common, so that the same p− type diffusion region is used common to the LDD region 11b and the LDD region 11c. 
A silicide layer 14A is formed on the poly silicon gate electrode 13A and a silicide layer 14B is formed on the poly silicon gate electrode 13B. Further, sidewall insulating films are formed on sidewalls of the poly silicon gate electrode 13A and the poly silicon gate electrode 13B, respectively.
Further, p+ type diffusion regions 11e and 11f are formed outside of the sidewall insulating films of the poly silicon gate electrode 13A in the silicon substrate 11, and also p+ type diffusion regions 11g and 11h are formed outside of the sidewall insulating films of the poly silicon gate electrode 13B in the silicon substrate 11. The diffusion region 11f and 11g are configured by the same p+ type diffusion region.
Further, a SiON (silicon oxynitride) film 15 is formed on the silicon substrate 11 for covering both the poly silicon gate electrode 13A with its sidewall insulating films and the silicide layer 14A and the poly silicon gate electrode 13B with its sidewall insulating films and the silicide layer 14B. A first interlayer insulating film 16 made of SiO2 is formed on the SiON film 15. Contact holes 16A, 16B, and 16C are formed in the first interlayer insulating film 16 for exposing the surfaces of the diffusion regions 11e, 11f (in common with 11g), and 11h. W (tungsten) via plugs 17A, 17B, and 17C are formed through intermediate layers 17a, 17b, and 17c formed by stacking a Ti (titanium) film and a TiN (titanium nitride) film in the contact holes 16A, 16B, and 16C, respectively.
On the first interlayer insulating film 16, a first ferroelectric capacitor C1 is formed by a sandwich film of a lower electrode 18A, a poly ferroelectric film 19A and an upper electrode 20A, contacting the W plug 17A. Likewise, a second ferroelectric capacitor C2 is formed by a sandwich film of a lower electrode 18C, a poly ferroelectric film 19C and a upper electrode 20C contacting the W plug 17C.
Further, a hydrogen barrier film 21 made of Al2O3 is formed on the first interlayer insulating film 16 for covering the ferroelectric capacitors C1 and C2, and a second interlayer insulating film 22 is formed on the hydrogen barrier film 21.
Further, a contact hole 22A exposing the upper electrode 20A of the ferroelectric capacitor C1, a contact hole 22B exposing the W via plug 17B, and a contact hole 22C exposing the upper electrode 20C of the ferroelectric capacitor C2 are formed in the second interlayer insulating film 22. For the contact holes 22A, 22B, and 22C, W plugs 23A, 23B, and 23C are formed through individual contact films 23a, 23b, and 23c, respectively, formed by a sandwich film of a Ti film and a TiN film.
A1 wiring patterns having Ti/TiN stacked structures 24A, 24B, and 24C, are formed on the second interlayer insulating film 22, where individual wiring patterns correspond to W plugs 23A, 23B, and 23C, respectively.
The orientation of the ferroelectric films 19A and 19C in the ferroelectric capacitors C1 and C2 is an important characteristic for ferroelectric memory devices.
A perovskite film such as PZT (Pb (Zr, Ti) O3) belongs to a tetragonal group. Self-orientation determines a ferroelectric property of a crystal, and the ferroelectric property is induced by displacement of Zr or Ti atoms in c-axis directions of a crystal lattice. It is suitable for the c-axes of individual crystal grains in a ferroelectric film to be parallel to an applied electric field, when a capacitor insulating film of a ferroelectric capacitor is formed of a perovskite film. Therefore, it is preferable for the orientation to be perpendicular ((001) orientation) to a plane of the capacitor insulating film. In contrast, it is difficult to induce a desired self-orientation by applying bias voltage to the capacitor if the orientation of the c-axis of the capacitor insulating film is distributed in a plane ((100) orientation).
However, although a perovskite film belongs to a tetragonal group, the probabilities for obtaining (001) orientation grains and (100) orientation grains are similar in a PZT film formed by a conventional fabrication technique, because the angle of the c-axis is similar to that of the a-axes in a perovskite film. If taking account of a number of other orientations, a small portion ratio of all the grains in the film would contribute to actual operation of the ferroelectric capacitor. Because of these issues, in the ferroelectric memory device technology, ferroelectric films 19A, 19C are formed to obtain approximately (111) orientation films and arranged in a <111> direction by bias voltage so that a relatively large switching electronic charge Qsw is obtained.
To achieve the orientation of a ferroelectric film, it is important to control the orientation of the lower electrodes 18A and 18C. Thereby, a Ti film is used for obtaining self-orientation as an orientation control film. A metallic film or a conductive oxide material, such as an Ir film, a Pt film, an IrOx film, or a RuOx film, is used as an orientation control film having (111) orientation. A Ti film indicates (002) orientation.
On the other hand, for a case where a Ti film is used as an orientation control film, as shown in FIG. 1, when a Ti film is deposited on a film such as a silicon dioxide film, the Ti atoms are immediately tightly bound with oxygen atoms, as shown in FIG. 2, because Ti atoms of the Ti film are highly reactive with oxygen atoms exposed on a surface of a film that has oxygen atoms on its surface. As a result, the degree of the self-orientation is reduced because the self-orientation requires free Ti atoms moving on the film surface. This reduces the proportion of desired (002) orientation grains of a formed Ti film. Further, in some cases, the c-axis of crystal grains of a Ti film obliquely aligns to a main plane of a silicon oxide film 16. As a result, many crystal grains having undesired orientation (not aligned to (002) orientation) are formed.
Patent document 1 describes that when the contact plugs 17A-17C of FIG. 1 have been formed, the surface of the interlayer insulating film 16 is processed by NH3 plasma treatment as shown in FIG. 3 so that NH groups are bound with oxygen atoms at the surface of the interlayer insulating film 16.
According to the above configuration, even if a Ti film is deposited on the interlayer insulating film 16, Ti atoms on the film are not captured by oxygen atoms as shown in FIG. 4 and freely move on the surface of the interlayer insulating film 16. As a result, a self-oriented Ti film having (002) orientation is formed on the interlayer insulating film 16.
In succession, the lower electrodes 18A and 18C are formed on the Ti film by the above technique, and followed by formation of ferroelectric films 19A and 19C, respectively, on the film. Thus a ferroelectric film dominated by crystal grains having (111) orientation may be obtained.
However, for the technique described in Patent document 1, as the lower electrode 18A or 18C is directly formed on the W plug 17A or 17C, the crystal direction of the W plug 17A or 17C formed of poly crystal metal such as poly crystal tungsten, may still maintain its influence, even when NH3 plasma treatment is performed. Therefore, controlling the self-orientation of a Ti film for most of the ferroelectric film 19A or 19C is not effectively achieved.                Patent document 1: Japanese Patent Application Publication 2004-153031        Patent document 2: Japanese Patent Application Publication H8-76352        Patent document 3: Japanese Patent Application publication 2001-149423        